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Issue 1, Volume
6, January 2009
Title of the Paper: Forms, Solutions and
Effects Regarding Pattern Resistant Logic
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Authors: Mirella Amelia Mioc
Abstract: Built-in self-tests are the heart of any modern reliability tests.
Their applications are ranging from cryptography and bit-error-rate
measurements, to wireless communication systems employing spread spectrum or
code division multiple access techniques. However the strict time constraints
limit the complexity of the tests as such, that multiple compression methods
via a parallel LFSR (Linear Feedback Shift Register) signature analyzer exist.
This paper’s purpose is to raise awareness of the issue to propose a common
framework for the identification of pattern resistant logic as well as a means
to ensure a more stable and safe fault tolerance using a ROM (Read Only
Memory) memory as a look-up table. The alternative proposed method for
implementing BIST (Built In Self Test) avoids the use of advanced compression
algorithms and needs very little hardware overhead so having small cost and
die size.
Keywords: Linear Feedback
Shift Register, Built In Self Test, Random Pattern Resistant, Pattern
Resistant Logic, Level-Sensitive Scan Design, Digital Signature, Cryptosystem,
Very High Speed Integrated Circuit Hardware Description Language,
Multiple-Input Signature Register, Look-Up Table
Title of the Paper: A Multiplier Based
on the Algorithm of Chinese Abacus
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Authors: Chien-Hung Lin, Shu-Chung Yi, Jin-Jia Chen
Abstract: A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese
abacus. As comparing the simulation result of this work with the speed of the
4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus
multiplier are 14% and 7.5% less than that of Braun array multiplier with
0.35?m and 0.18?m technologies, respectively. Meanwhile, the power consumption
of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3%
also.
Keywords: Braun array
multiplier, Chinese abacus multiplier, fast multiplier
Title of the Paper: Modelling and
Simulation of Step-Up and Step-Down Transformers
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Authors: Marius-Constantin Popescu, Nikos Mastorakis
Abstract: The current and power (active and reactive parts) at the terminals
of the step-down transformer are positive if the transit is in line busbar to
charge. The study of the dynamic behavior of the system developed in the
later, will use numerical simulations and the calculation of eigen values.
Keywords: Step-up and
step-down transformers, Power model and current
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