WSEAS CONFERENCES. WSEAS, Unifying the Science

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Oct. 2007, Nov. 2007,Dec. 2007, 2008


Issue 12, Volume 6, December 2007
ISSN: 1109-2734 E-ISSN: 2224-266X








Title of the Paper:  FPGA Design, Implementation and Analysis of Scalable Low Power Radix 4 Montgomery Multiplication Algorithm


Authors: A. A. Ibrahim, H. A. Elsimary, A. M. Nassar

Abstract: This paper proposes an efficient algorithm and Processing Element (PE) architecture for a Multiple Word Radix 4 Montgomery Modular (MWR4MM) multiplier. This architecture is developed considering an important design factor - power consumption - in addition to other design factors that is considered previously in many publications such as performance and scalability. To increase performance, we used a recoding scheme that eliminates the reduction step in the Montgomery algorithm and the PE architecture is based on the Carry-Save Adder (CSA). To achieve scalability, we implement the algorithm based on the multiple-word operation. Lastly to lower power consumption, we devised several effective techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals.

Keywords: Montgomery multiplication, Scalability, Cryptography, Secure communications, Low power modular multipliers

Title of the Paper: A Low-Power Scheduling Tool for System On a Chip Designs


Authors: Ali Mahdoum, Nadjib Badache, Hamid Bessalah

Abstract: As semiconductor technology scales down, integration on a chip becomes higher and concerns complex algorithm implementation. Those algorithms concern plenty of applications in many fields. Thus, adequate scheduling techniques that cope with such a variety of applications are required. The method presented in this paper addresses that concern and takes advantage of both data flow and control flow approaches. Knowing that such a Controlled Data Flow Graph (CDFG) scheduling is not polynomial, an efficient heuristic-based approach is then needed. In addition, because time and resources are user-constraints that gain a particular attention, our heuristic-based method targets a minimal number of cycles. More, it detects exclusive operations of the same type that can be scheduled in the same control step and share the same resource. Because the power dissipation is a crucial problem for SOC designs, our tool automatically introduces additional constraints so that the switching power dissipation at a high design level is reduced.

Keywords: CDFG; scheduling; heuristic; user constraints; variety of domain applications; low power design, efficient cycle number, high design level, SOC designs

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